The present invention relates generally to a method and system for computer aided design (CAD) of integrated circuits and in particular to reproducing prototyping failures in emulation.
Application specific integrated circuits (ASIC) and system on chip (SoC) integrated circuits (ICs) have become more complex and difficult to validate or test by software simulation alone. Hardware assisted circuit design verification overcomes some of these software simulation difficulties. Two types of hardware assisted circuit design verification include prototyping and emulation. Designers build boards called prototypes including field programmable gate array (FPGA) ICs. The circuit design represented as hardware description language (HDL) is compiled and programmed into the FPGAs, which provide a hardware implementation of the circuit for testing. Prototypes provide the best runtime performance, i.e. high speed, among all the available present verification technologies. Higher speed allows designers to validate very complex chip designs. The input to a prototype may be connected to real time signal sources such as a universal serial bus (USB), Ethernet, or the like, to verify the circuit's functions. Prototyping however has two major limitations; long time to bring up, i.e. long time to have a working model, and limited runtime debugging.
Emulation is faster to bring up, provides greater debugging capability, but has slower performance than prototyping. Unlike prototypes, emulators include elaborate runtime/firmware support, which sacrifices performance for debugging, and have fixed interconnects between processing elements. The debug support requires a software stack that is capable of mapping user signals to their location in the physical device, which models the user design.
Accordingly, there is a need for a hardware assisted circuit design verification method and system having the advantages of high speed prototyping, while preserving the faster time to bring up and better debugging capability of emulation.